A Universal Test Pattern Generator for DDR SDRAM
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چکیده
Because the memory cores can be used to save the instructions/data, the memory cores are frequently used within the system-on-a-chips (SOCs). The quality of the SOCs is mainly determined by the memory cores. However, due to the complicated fabrication process, the fault models of the memories are more complicated than the fault models of the logical cores. So far, more than 40 march algorithms have been proposed; however; no any single march algorithm can be _________________________________________ *This work was supported in part by the National Science Council of R.O.C. under contract NSC 91-2215-E-230-003. used to detect all the faults. To test effectively the memories, at least two march algorithms are used, however increasing the hardware cost. The double data rate synchronous dynamic random access memory (DDR SDRAM) is one of the promising memory products of today. To meet the market requirements, various specifications of DDR SDRAMs are manufactured. In this paper, a universal test pattern generator has been proposed for testing the various DDR SDRAMs.
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تاریخ انتشار 2003